Field of the Invention
The invention relates to an electrically programmable memory cell configuration, and to a method for producing an electrically programmable memory cell configuration.
An electrically programmable memory cell configuration, or so-called EEPROM configuration, has transistors which may each have at least two different threshold voltages. In order to read information, which is stored in one of the transistors, a voltage, which is between the two threshold voltages, is applied to a control gate electrode of the transistor. Depending on whether the threshold voltage of the transistor is less than or greater than the voltage on the control gate electrode, a current will or will not flow through the transistor. The information is stored in the form of the threshold voltage of the transistor and represents a logic variable "0" or "1".
In order to allow information to be stored, that is to say in order to make it possible to set the appropriate threshold voltage, an electrically insulated floating gate electrode is arranged between the control gate electrode and a channel region of the transistor. The threshold voltage of the transistor can be varied by varying the charge on the floating gate electrode. The charge on the floating gate electrode is varied by electrons which, due to a voltage drop between the control gate electrode and the channel region or a source/drain region of the transistor, tunnel through a thin dielectric or overcome the potential barrier of the dielectric. The term "floating gate electrode" refers to the fact that a floating gate electrode is not connected to a potential, and therefore "floats".
If, when voltage is applied, the electrons tunnel through the thin dielectric into the floating gate electrode, then this is referred to as Fowler-Nordheim tunneling (see S. M. Sze, Physics of Semiconductor Devices, J. Wiley & Sons, N.Y. 1981, page 497). If, on the other hand, storage is carried out on the basis of a high current through the transistor, that is to say if there is a high voltage drop between the source and the drain, then hot electrons can be injected into or out of the floating gate electrode. An injection mainly occurs in the vicinity of the drain region, since the voltage drop is particularly high there.
Transistors which are adjacent along a bit line can be connected in series (NAND architecture) or parallel (NOR architecture).
In VLSI (very-large-scale integration) technology, it is desirable to increase the packing density of circuit configurations, in order to reduce process costs and to increase switching speeds.
Published German patent application DE 19524478 A1 describes an EEPROM configuration using a NOR architecture, in which vertical MOS transistors are arranged on flanks of trenches which run parallel to one another in a substrate. The flanks are formed with a first dielectrics. Bit lines run along the bottoms of the trenches and between the trenches, and word lines run transversely with respect to the bit lines. Floating gate electrodes and control gate electrodes, which are separated by second dielectrics from the floating gate electrodes, are arranged in the trenches. In order to keep any voltage drop between the control gate electrodes and the floating gate electrodes small, and thus to reduce the operating voltage, the extent of the floating gate electrodes in the vertical direction is greater than the depth of the trenches, and the floating gate electrodes project beyond a main surface of the substrate. The packing density is not reduced by the vertical extent. However, the structure of the floating gate electrodes reduces the process reliability, since the thin projecting parts of the floating gate electrodes are not mechanically robust. A cell area of 2F.sup.2 can be achieved with this configuration, where F is the minimum structure size which can be produced lithographically using the respective technology.
According to published German patent application DE 19524478 A1, in the case of Fowler-Nordheim tunneling, two transistors in an EEPROM configuration, which share a bit line, would be programmed at the same time and therefore, such an EEPROM configuration could be programmed only by the injection of hot electrons. In this case, a part of the bit lines are at one potential and another part of bit lines are at a different potential, with a voltage drop being present between adjacent bit lines only for the transistor that is to be programmed. Programming by injection of hot electrons is disadvantageous since high programming currents, and thus high power levels, are required.
The article "A Novel NOR Virtual-Ground Array Architecture for High Density Flash", by Y. Yamauchi et al., in the Extended Abstracts of the 1996 International Conference on Solid State Devices and Materials, Yokohama, 1996, pages 269 to 271, proposes an EEPROM configuration with planar transistors and using NOR architecture in which programming can be carried out via Fowler-Nordheim tunneling despite adjacent transistors having common bit lines. For this purpose, the bit lines each have a first section and a second section with the first section being doped at a lower concentration than the second section. Since there is a voltage drop to the tunnel oxide in the first part of a bit line, only the floating gate electrode which is adjacent to the second part of the bit line is programmed. A cell area of 5F.sup.2 can be achieved with this configuration.
In order to keep any voltage drop between the control gate electrode and the floating gate electrode small, and thus to reduce the operating voltage, H. Shirai et al. propose a memory cell configuration in the article "A 0.54 .mu.m.sup.2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256 Mbit Flash Memories", IEDM, Technical Digest, IEEE, New York, 1995, pages 653 to 656. In this memory cell configuration the capacitance which is formed by the control gate electrode and the floating gate electrode is increased by using hemispherical-grained polysilicon as the material for the floating gate electrode. The hemispherical-grained polysilicon provides an increased surface area of the floating gate electrode and thus an increased coupling area between the floating gate electrode and the control gate electrode.